Job Title:
ASIC Design and Verification Engineer (3390)



Company:
QLogic



Location:
Shakopee



Status:
Full Time, Employee



Job Category:
Other













QLogic Corporation (Nasdaq:QLGC) simplifies the process of networking storage for OEMs, resellers and system integrators. With the vision of a SAN in every business, QLogic produces the controller chips, host bus adapters (HBAs) and fabric switches that are the backbone of storage networks for most Global 2000 corporations. The company serves customers with solutions based on all storage network technologies including SCSI, Internet SCSI (iSCSI) and Fibre Channel.








ASIC Design and Verification Engineer (3390)

Description

QLogic simplifies the process of networking storage by providing easy to use high performance SAN products of exceptional quality. QLogic produces the controller chips, host bus adapters (HBA's), fabric switches and management software that are the backbone of storage networks for most Global 2000 corporations as well as small and medium businesses. QLogic builds solutions based on all storage network technologies including SCSI, iSCSI, Inifiband, FCoE and Fibre Channel.

We are currently looking for an ASIC Design and Verification Engineer at our Shakopee, Minnesota facility. Job responsibilities include:

• Design blocks of logic using Verilog or VHDL hardware languages

• Analyze functional specifications and test plans in order to develop unit simulation test benches for ASIC verification

• Investigate performance improvements

• Investigate area and power reductions

• Support timing closure of physical design

This position requires independent thinking to resolve issues associated with the design and test of complex ASICs. In addition, the job requires approaching design and problem resolution with exacting precision and attention to detail to continue a strong history of first pass success. All tasks are completed in a team environment using state of the art simulation and analysis tools.



Required Skills

• Bachelors or Masters in Electrical Engineering

• Minimum 6 years of experience with ASIC design

• Design experience of storage or networking products

• Several completed projects using high speed logic design

• Fluent in Verilog or VHDL

• Experience with synthesis and static timing tools

• Experience in developing or debugging hardware and software

• Experience with typical lab equipment such as logic analyzers, oscilloscopes, in-circuit emulators (ICE), etc.

• Knowledge of networking or system I/O protocols such as SCSI, Fibre Channel, SAS, or Ethernet

• Familiarity with assembly and/or low level hardware coding (setting bits, and writing bytes to initialize and configure ASIC's for test operations)

• Ability to read and use scripting languages such as BASH PERL or TCL

• Familiar with board level design