Secret clearance: ACTIVE/INTERIM_must have ability to get a clearance, but not needed to start

Work Status: US CIT/Perm Res/Greencard/Visa___U.S. Citizens Only____________________________

The successful candidate will be responsible for:

·         Working with a team of development engineers and leading an FPGA implementation (using System Generator) of a waveform designed and simulated with Matlab and Simulink

·         Working with system engineers, business development managers, and program managers to define and review the system requirements affecting the FPGA design

·         Documenting key design alternatives as well as the final FPGA design

·         Assisting in debugging the overall FPGA design and optimize the design for throughput

·         Participating in the FPGA design reviews to ensure best practices are followed

·         Mentoring junior engineers in FPGA design best practices as well as tradeoffs when optimizing for speed, area or power

Preferred skills and experience:

·         VHDL, Matlab, Simulink, ModelSim, ISE Foundation and ChipScope

·         10+ years FPGA design experience

·         5+ years General DSP design experience

·         3+ years experience with Xilinx’s System Generator for DSP

·         In-depth knowledge of Xilinx’s Virtex 4 architecture (including the SX family)

·         Leonardo and Synplicity Synthesis Tools

·         BS or MS in EE or CE