4-6 months could go longer
Cary, NC
IC layout
IC Layout on TSMC 28nm CMOS process. Cell & transistor level layout, block and chip level integration.
Necessary Skills (Must Have):
IC layout on TSMC 45nm or lower CMOS process. Cell & transistor level layout, block and chip level integration. Be able to run Calibre DRC/LVS standard tool.