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Physical Design Engineer, STA ...


Job Summary

A New Beginning-Genesis 2
Multiple locations
Electronics, Components, and Semiconductor Mfg
Job Type
Full Time
Years of Experience
5+ to 7 Years
Education Level
Bachelor's Degree
Career Level
Experienced (Non-Manager)
0.00 - 135,000.00 $ /year
great bennies, perks, 20 % bonuses

Physical Design Engineer, STA or static timing analysis; we use a tool called Primetime

About the Job

Please do not respond via the monster message center, please email me directly if it is not too much trouble - joseph8601@sbcglobal.net

Please feel free to call 860 889 4141, until 9 PM Eastern, 7 days a week, including most weekends and holidays, after you email a word doc resume directly to me from your own email, and I will help you - joseph8601@sbcglobal.net

Physical Design Engineer

The key to this job is STA or static timing analysis;  we use a tool called Primetime

You will be responsible for all aspects of physical implementation from RTL to GDS, including  RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout.   Interface with other design groups to ensure time to market and quality of results. You will also participate in design/architecture reviews, establishing & defining physical design methodologies and flow automation.

Base Salary - $95,000 to $135,000
Benefits - Full
Relocation Assistance Available - Yes
Bonus Eligible - Yes
Additional Compensation - $5,000 to $20,000

5+ to 7 years experience
Minimum Education - Bachelor's Degree

Skills and Certifications-required
worked on/written timing constraints
experience with clock tree synthesis
scan insertion' dft
rtl logic

Ideal Candidate, This position requires a BSEE/MSEE and 5+ years industry experience in a Logic design or Physical Design position.  Candidate should preferably have strong knowledge of RTL design and must be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter, Primetime, Conformal LEC, and ATPG. Ideal candidate will also have working knowledge of scan insertion, and ATPG.  Must have good communication, teamwork, and debug/analysis skills for designs, library and technology files.

Also, please understand this may take time for both of us working together to help advance your career. I will do my best for you and never charge you anything for our time and efforts

In all cases we always have several jobs not yet published on the WWW, listed on linkedin or posted to our company website

Many full job descriptions and base salaries in your field of experience can be viewed in various sections on -

A New Beginning-Genesis 2
Regards, SHALOM, ciao, Namaste, Peace,
Joseph Anthony Vaccariello


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