Zarlink Semiconductor is actively seeking a senior analog designer to join the Analog Design group.  The Analog Design team develops the critical IP blocks used in the Zarlink timing products. These circuits include multi-GHz PLL circuits and high speed IO pads.

As a senior analog designer the individual will:

•  Develop critical analog IP blocks such as PLL that will be embedded in Zarlink Semiconductor designs
• Be expected to be involved in all aspects of the analog design process from schematic design to validation of circuits in the lab.
• Provide input to system and chip architects on technology selection, performance limits, area and power analysis for analog blocks.
•  Provide guidance and coaching to junior analog engineers and test engineer for production test programs.

Qualifications:         

• 10 years of high speed / RF design experience
• In-depth implementation knowledge of various PLL architectures
• Proven experience in leading design, verification and optimization of APLL top level architecture and sub-modules
• Analog layout experience for low noise, RF circuit in mixed signal context
• Knowledge of integrated circuit, device physics and advanced process technology
• Exposure to digital design
• Excellent lab, data acquisition and data analysis experience
• Cadence analog / mixed signal simulation tools
• CAD set up environment, skill routines, scripts
• MS or PhD in EE with more than 15 years experience in analog IC design.
• Must have a passion for his/her work and be a team player. Team lead experience preferred.

Apply here:  http://ottdom01.zarlink.com/hr_kan/recruitmentWeb.nsf/frmJobFinder?OpenForm